The invention relates to an integrated dynamic memory cell having a small area of extent, which is integrated in a trench which is etched in a substrate.
A dynamic semiconductor memory contains a large number of memory cells. A conventional memory cell has a memory capacitance that can be connected to a bit line via a selection transistor. If a high voltage level is applied to a word line, then the selection transistor conducts, and the memory capacitance is connected to the bit line. In this state, a data item can be written to the memory cell by the capacitance being charged or discharged to the desired memory content.
In order to provide dynamic memories with a memory capacity in the Gigabit range, a large number of memory cells must be integrated on the substrate chip area. Since the substrate chip area is limited, it is necessary to keep the area of extent of an individual integrated dynamic memory cell as small as possible. Miniaturization is in this case also governed by the lithographic technique used. The lithographic technique used defines a minimum lithographic structure size F, which is currently approximately 150 to 200 nm.
One disadvantage of the conventional memory cell is that the capacitance of the memory capacitor cannot be reduced as integration to form smaller structures increases. European Patent EP 0 537 203 B1 proposes a memory cell with two MOSFET transistors. However, the area of extent of the memory cell described there is relatively large, since the memory cell is formed in a planar fashion on the substrate surface.
It is accordingly an object of the invention to provide an integrated dynamic memory cell having a small area of extent, and a method for its production that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated dynamic memory cell having a small area of extent. The memory cell is formed of a semiconductor substrate having a trench formed therein and defined by a bottom and side walls, including a first side wall and a second side wall opposite the first side wall. A selection MOSFET is disposed on the first side wall of the trench. The selection MOSFET has a gate connection area that is to be connected to a word line, a source connection doping area which is to be connected to a bit line, and a connection doping area forming the bottom of the trench and a drain connection doping area of the selection MOSFET. A thin dielectric layer is provided. A memory MOSFET is disposed on the second side wall of the trench and has a source connection doping area, a gate connection area which is connected through the thin dielectric layer to the connection doping region. The connection doping region connects the source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area which is to be connected to a supply voltage. A connecting area formed from n-polysilicon is connected to the thin dielectric, and tunnel currents flowing through the thin dielectric layer can be varied by a doping of the connecting area and by a doping of the connection doping region. The thin dielectric layer has a thickness of less than two nm so that the tunnel currents flow between the gate connection area of the memory MOSFET and the connection doping region.
In one preferred embodiment of the dynamic memory cell according to the invention, the selection MOSFET and the memory MOSFET are each NMOS transistors.
In a further preferred embodiment of the memory cell according to the invention, the thin dielectric layer has a thickness of less than 2 nm, so that tunnel currents can pass through the thin dielectric layer.
In a further preferred embodiment, the tunnel currents which flow through the thin dielectric layer can be varied by the doping of the gate connection area and of the connection doping region.
The thin dielectric layer preferably has an asymmetric current flow characteristic similar to that of a diode.
The thin dielectric layer is preferably composed of an oxide, nitride or oxynitride.
In a further preferred embodiment of the dynamic memory cell according to the invention, the selection MOSFET and the memory MOSFET each have a gate oxide layer, and these layers run along the sidewalls of the etched trench.
In a further embodiment of the dynamic memory cell according to the invention, the gate connection areas of the selection MOSFET and of the memory MOSFET are formed by spacers.
In one preferred embodiment, the source connection areas and the drain connection areas of the two MOSFETs, and the connection doping region, are doped by ion implantation.
In a further preferred embodiment of the dynamic memory cell according to the invention, doped current-conductive channels are located alongside each of the gate oxide layers of the selection MOSFET and of the memory MOSFET and their doping can be varied in order to fix the respective switch-on voltage of the two MOSFETs.
The doped current-conductive channels are preferably doped by ion implantation.
In one particularly preferred embodiment of the dynamic memory cell according to the invention, a width of the etched trench corresponds to the minimum lithographic structure size.
The length of the doped current-conductive channels in this case preferably corresponds essentially to the depth of the etched trench.
In a further embodiment of the dynamic memory cell according to the invention, a depth of the etched trench is greater than the width of the etched trench.
The gate connection area of the selection MOSFET of a dynamic memory cell is preferably formed by a spacer that runs continuously in the etched trench and forms the gate connection area for a large number of further selection MOSFETs of other dynamic memory cells.
In a further embodiment of the memory cell according to the invention, the area of extent of the dynamic memory cell corresponds approximately to four times the square of the lithographic structure size.
Semiconductor substrate areas of selection MOSFETs of different memory cells that are disposed on one sidewall of the etched trench are preferably disposed such that they are separated from one another by insulation layers.
In a further preferred embodiment of the dynamic memory cell according to the invention, the semiconductor substrate areas of memory MOSFETs, which are disposed on an opposite side of the etched trench, are likewise separated from one another by insulation layers.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing an integrated dynamic memory cell. The method includes the steps of:
a) providing a semiconductor substrate having a surface;
b) implanting the surface of the semiconductor substrate;
c) etching a trench in the semiconductor substrate;
d) implanting the semiconductor substrate at a bottom of the trench to form a drain connection doping area and a connection doping region;
e) thermally oxidizing two side walls of the trench to form dielectric layers on the side walls functioning as gate insulation layers for a selection MOSFET and a memory MOSFET;
f) depositing an insulating oxide layer on the bottom of the trench;
g) forming polysilicon spacers on the side walls of the trench, the polysilicon spacers functioning as gate electrodes for the selection MOSFET and the memory MOSFET;
h) etching the insulating oxide layer with the polysilicon spacers which have been formed as masks, and with a central surface area of the semiconductor substrate that has been implanted being exposed;
i) filling one of a right-half and a left-half of the trench with an insulating material;
j) depositing a thin dielectric layer, through which tunnel currents can pass, on a remaining exposed half of the central surface area of the semiconductor substrate on the bottom of the trench; and
k) depositing a polysilicon layer on the thin dielectric layer.
The method according to the invention provides a self-amplifying dynamic memory cell that requires only a very small area. The production process in this case is particularly simple, since the masks that are formed are in the form of strips, thus further simplifying the photolithography. Since the etched trench for accommodating the MOSFETs in the memory cell can be relatively deep, the current-conductive channels of the MOSFETs are also relatively long, so that leakage currents, which can flow away via the selection transistor, are particularly low. The asymmetric current flow characteristic resulting from the tunnel currents through the thin dielectric layer can be varied by the doping of the adjacent doped layers. In consequence, the dynamic response of the memory cell can be influenced appropriately for the desired application.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated dynamic memory cell having a small area of extent, and a method for its production it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.